1. Technical Field
The present invention relates generally to memory management; and, more particularly, it relates to packet-based direct memory access.
2. Related Art
Direct Memory Access (DMA) is a special hardware added to many computer systems to allow data transfers between memory and an input/output (I/O) device being handled without intervention by the central processing unit (CPU). Typically, the CPU will first set up the DMA controller (DMAC) by programming some registers containing a memory address and the transfer length (number of bytes to be transferred). The DMAC behaves as a bus master and the I/O device provides transfer controls to the DMAC in forms of predefined commands. To effectively utilize the bus bandwidth and minimize the software overhead, several DMA architectures were invented. Two such examples of DMA architectures are described in xe2x80x9cDescriptor Based DMA Architecture,xe2x80x9d Apple computer and in xe2x80x9cDescriptor-Based DMAxe2x80x9d, IBM RS/6000.
These conventional and traditional methods generally use descriptors to provide control information (e.g., the transfer length) to the I/O device. These conventional methods are most effective for transfers with longer block lengths, like in many stream-based communications. However, its advantage diminishes as the transfer length is shortened. In most of asynchronous transfer mode (ATM) cell-based asynchronous digital subscriber loop (ADSL) applications, data are transferred in number of fixed-length packets within a computer system. The packets are typically 56 or 64 bytes in size. The packets will eventually be converted to 53-byte cells for transmission over an ATM communication channel. Those solutions employed using a universal serial bus (USB) are also packet-based. The transfer control in the conventional manner of DMA described above inherently requires descriptor information.
The descriptors employed in conventional DMA include any number of various types of information. For example, a beginning address, a data transfer byte length, or a receive data byte count, DMA control status, and other information necessary to perform conventional DMA can be very large in terms of size and very complex in terms of implementation. Other DMA methods, including scatter-gather DMA systems additionally require even more information in their descriptors, enabling the gathering of various portions of data from various locations in the memory.
Further limitations and disadvantages of conventional and traditional systems will become apparent to one of skill in the art through comparison of such systems with the present invention as set forth in the remainder of the present application with reference to the drawings.
Various aspects of the present invention can be found in a packet-based direct memory access system. The packet-based direct memory access system includes a microchip circuitry, a number of registers including an increment register, a decrement register, and a pending register, and a flow control state machine. The microchip circuitry contains the registers, and it is operable to perform direct memory access of packet-based data. The packet-based data is either transferred to the device from the microchip circuitry to the device or received by the microchip circuitry from the device. The packet-based data is broken into a number of fixed length packets. The flow control state machine is operable control whether a packet is transmitted to the device from the microchip circuitry or whether a packet is received by the microchip circuitry from the device. The flow control state machine is operable to modify values stored in the increment register and the pending register during the transmission to the device from the microchip circuitry. The flow control state machine is also operable to modify values stored in the decrement register and the pending register during the receipt by the microchip circuitry from the device.
In certain embodiments of the invention, the flow control state machine is operable to control an increase of a value stored in the transmit pending register by a value stored in the increment register when no packet is transmitted to the device from the microchip circuitry and the increment register is updated. The flow control state machine is operable to control a decrease of a value stored in the transmit pending register by one when a packet is transmitted to the device from the microchip circuitry and the increment register is not updated. The flow control state machine is also operable to control a decrease of a value stored in the transmit pending register by a predetermined value and increases the value stored in the transmit pending register by a value stored in the increment register when a packet is transmitted to the device from the microchip circuitry and the increment register is updated.
The flow control state machine is operable to control a decrease of a value stored in the receive pending register by a value stored in the decrement register when no packet is received by the microchip circuitry from the device and the decrement register is updated. The flow control state machine is operable to control an increase of a value stored in the receive pending register by one when a packet is received by the microchip circuitry from the device and the decrement register is not updated. The flow control state machine is also operable to control an increase of a value stored in the receive pending register by one and decreases the value stored in the receive pending register by a value stored in the decrement register when a packet is received by the microchip circuitry from the device and the decrement register is updated.
The microchip circuitry also includes a direct memory access interface and the flow control state machine itself. The direct memory access interface is operable to perform receipt of the packet-based data by the microchip circuitry from the device as well as transmission of the packet-based data from the microchip circuitry to the device. The device is any number of devices including an asynchronous digital subscriber loop modem. In various embodiments of the invention, the microchip circuitry also includes a system bus to which a number of system devices are communicatively coupled, and a peripheral bus. A communication interface circuitry is communicatively coupled to the peripheral bus. The communication interface circuitry itself contains a direct memory access interface and the flow control state machine.
The packet-based data is any type of packet-based data including asynchronous transfer mode cell-based asynchronous digital subscriber loop data and universal serial bus data.
Other aspects of the present invention can be found in a packet-based direct memory access system. The packet-based direct memory access system includes a direct memory access interface, a flow control regulator, and an increment register, a decrement register, a transmit pending register, and a receive pending register. The direct memory access interface is operable to transmit and receive packet-based data to and from a device. The flow control regulator is communicatively coupled to the direct memory access interface and is operable to control the state of receipt of a packet of the packet-based data and transmission of a packet of the packet-based data. The flow control regulator uses the increment register and the transmit pending register to determine how to control transmission of a packet of the packet-based data, and the flow control regulator uses the decrement register and the receive pending register to determine how to control receipt of a packet of the packet-based data.
The device is any number of devices including an asynchronous digital subscriber loop modem. The flow control regulator employs a hardware assisted handshaking protocol engine to obviate the need for descriptors in performing the packet-based direct memory access. The packet-based direct memory access system includes a microchip circuitry that itself contains a communication interface circuitry. That communication interface circuitry includes the direct memory access interface circuitry and the flow control regulator. The flow control regulator is a flow control state machine in some embodiments.
The packet-based data is any type of packet-based data including asynchronous transfer mode cell-based asynchronous digital subscriber loop data as well as universal serial bus data.
Other aspects of the present invention can be found in a method to perform packet-based direct memory access. The method involves determining whether a packet of the packet-based data has been transmitted, determining whether a packet of the packet-based data has been received, selectively controlling values stored in the increment register and a transmit pending register based on transmission of a packet of the packet-based data, and selectively controlling values stored in the decrement register and the receive pending register based on receipt of the packet of the packet-based data.
In certain embodiments of the invention, the method also involves determining when the increment register is updated, increasing a value stored in the transmit pending register by a value stored in the increment register when no packet is transmitted and the increment register is updated, decreasing a value stored in the transmit pending register by one when a packet is transmitted and the increment register is not updated, and decreasing a value stored in the transmit pending register by one and increasing the value stored in the transmit pending register by a value stored in the increment register when a packet is transmitted and the increment register is updated.
Moreover, the method may also involve determining when the decrement register is updated, decreasing a value stored in the receive pending register by a value stored in the decrement register when no packet is received and the decrement register is updated, increasing a value stored in the receive pending register by one when a packet is received and the decrement register is not updated, and increasing a value stored in the receive pending register by one and decreasing the value stored in the receive pending register by a value stored in the decrement register when a packet is received and the decrement register is updated.
The packet-based data is any type of packet-based data including asynchronous transfer mode cell-based asynchronous digital subscriber loop data as well as universal serial bus data.
Other aspects, advantages and novel features of the present invention will become apparent from the following detailed description of the invention when considered in conjunction with the accompanying drawings.